~Get Your Files Here !

  01 - Introduction and agenda

   001 Introduction_en.vtt

   002 Introduction to timing path and arrival time_en.vtt

   003 Introduction to required time and slack_en.vtt

   004 Introduction to basic categories of setup and hold analysis_en.vtt

   005 Introduction to data check and latch timing_en.vtt

   006 Introduction to slew, load and clock checks_en.vtt

  02 - First things first - Introduction to timing graph

   001 Convert logic gates into nodes_en.vtt

   002 Compute actual arrival time (AAT)_en.vtt

   003 Compute required arrival time (RAT)_en.vtt

   004 Compute slack and introduction to GBA-PBA analysis_en.vtt

   005 Convert pins to nodes and compute AAT, RAT and slack_en.vtt

  03 - Clk-to-q delay, library setup, hold time and jitter

   001 Introduction to transistor level circuit for flops_en.vtt

   002 Negative and positive latch transistor level operation_en.vtt

   003 Library setup time calculation_en.vtt

   004 Clk-q delay calculation_en.vtt

   005 Steps to create eye diagram for jitter analysis_en.vtt

   006 Jitter extraction and accounting in setup timing analysis_en.vtt

  04 - Textual timing reports and hold analysis

   001 Setup analysis - graphical to textual representation_en.vtt

   002 Hold analysis with real clocks_en.vtt

   003 Hold analysis - graphical to textual representation_en.vtt

  05 - On-chip variation

   001 Sources of variation - etching_en.vtt

   002 Sources of variation - oxide thickness_en.vtt

   003 Relationship between resistance, drain current and delay_en.vtt

  06 - OCV timing and pessimism removal

   001 OCV based setup timing analysis_en.vtt

   002 Setup timing analysis after pessimism removal_en.vtt

   003 OCV based hold timing analysis_en.vtt

   004 Hold timing analysis after pessimism removal_en.vtt

  07 - Conclusion

   001 Conclusion and next topics!!_en.vtt

  Bonus Resources.txt