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  01 - Introduction to the course

   001 Preview_en.vtt

   002 Sample program on edaplayground_en.vtt

  02 - Introduction to Verilog HDL

   001 Verilog fundamentals_en.vtt

  03 - VLSI design flow ( FPGA & ASIC)

   001 VLSI Design flow (FPGA & ASIC)_en.vtt

   002 FPGA vs ASIC_en.vtt

  04 - Three levels of verilog design Description

   001 Three levels of verilog design Description_en.vtt

   002 Example mux_2x1 with 3 abstracts models_en.vtt

  05 - Verilog Language constructs, Data types & Compiler Directives

   001 Language constructs -Comments, keywords, identifier, Number specific, Operators_en.vtt

   002 Datatypes - net,reg, integer, real, string, time, Parameter, Vector,Array,Memory_en.vtt

   003 Compiler Directives_en.vtt

  06 - Verilog Program structure

   001 Verilog Program Structure -Module_en.vtt

   002 Ports_en.vtt

   003 Port Connection Rules_en.vtt

   004 Design Methodologies Approaches_en.vtt

  07 - Gate level modeling

   001 Gate Level Model Introduction_en.vtt

   002 Example 4x1 Mux_en.vtt

   003 Example Full Adder_en.vtt

   004 Tri-state Buffers with Examples_en.vtt

   005 Array of Instance with example_en.vtt

  08 - Data flow modeling

   001 Data flow Modeling assign statement_en.vtt

   002 Operators_en.vtt

   003 Arithmetic Operators_en.vtt

   004 Logical Operators_en.vtt

   005 Example Full Adder Logical operators_en.vtt

   006 Example Full Adder Arithmetic operators_en.vtt

   007 Example Binary to Gray code converter_en.vtt

   008 Logical and , Logical or (&&, )_en.vtt

   009 Shift operators Leftright Shift_en.vtt

   010 Shifting without shift operator , just with concatenation operator_en.vtt

   011 Ternary operator Example 2x1 MUX, 4x1 MUX_en.vtt

   012 Relational operators Example Comparator_en.vtt

   013 Equality (==) , case Equality (===) operators_en.vtt

   014 Reduction operator Example Parity Generator_en.vtt

  09 - Behavioral Modeling

   001 Behavioral Modeling - Introduction_en.vtt

   002 Behavioral Modeling Constructs_en.vtt

   003 Procedural Blocks- initial & always_en.vtt

   004 Example Clock Generation_en.vtt

   005 Assignment Statements - Blocking & Non-blocking_en.vtt

   006 Mechanism in Non-blocking_en.vtt

   007 Concurrency_en.vtt

   008 Advantage of Non-blocking assignment Example swapping_en.vtt

   009 Advantage of Non-blocking assignment Example Pipelining_en.vtt

   010 if-else statement Example 4x1 Mux_en.vtt

   011 Case – statement Example 4x1 Mux_en.vtt

   012 Advantage of Case over if-else_en.vtt

   013 Loops while, for, repeat, forever_en.vtt

   014 Parallel blocks - fork-join_en.vtt

   015 Combinational Logic Circuit Examples 8x1 Mux_en.vtt

   016 Example 8x1 Mux using 4x1 mux and 2x1 mux_en.vtt

   017 Example AND gate using 2x1 Mux_en.vtt

   018 Example 1x8 Demux_en.vtt

   019 Example Full Adder & 4-bit Full Adder_en.vtt

   020 Example 3x8 Decoder and 3x8 Decoder using 2x4 decoder_en.vtt

   021 Example 8x3 encoder_en.vtt

   022 Example Priority encoder_en.vtt

   023 Example Seven Segment Display_en.vtt

   024 Example ALU_en.vtt

   025 Sequential Logic Circuits List of Examples_en.vtt

   026 Example D Flip Flop vs D-Latch_en.vtt

   027 Example Synchronous Reset D-Flip flop , Asynchronous Reset D-Flip flop_en.vtt

   028 Example T-Flip Flop_en.vtt

   029 Example Master-slave JK Flip Flop_en.vtt

   030 Example Counter_en.vtt

   031 Example UPDown Counter_en.vtt

   032 Example clock divider using counter- Divide by 2,4,8,_en.vtt

   033 Example Pulse Generator Mod-3 pulse generator_en.vtt

   034 Example Divide by 3 clock_en.vtt

   035 Example Ring Counter vs Jonson Counter_en.vtt

   036 Example Shift Registers SISO, SIPO, PISO,PIPO_en.vtt

   037 Example LFSR (Linear Feedback Shift Register)_en.vtt

   038 memory design_en.vtt

  10 - Switch level modeling

   001 Switch level modeling_en.vtt

  11 - Test bench

   001 Functional simulation_en.vtt

   002 Example - Test bench for counter design_en.vtt

   003 Example - Test bench for Pulse generator_en.vtt

  12 - Functions & Task and system tasks

   001 Functions & tasks and system tasks_en.vtt

   002 File based system tasks and random generator system task_en.vtt

   003 Read file and write in to memory system task_en.vtt

   004 Programming Language Interface_en.vtt

  13 - FSM

   001 FSM ( Finite State Machine) & Hardware modeling of FSM, Example Verilog code_en.vtt

   002 Example FSM - Divide by 2 clock_en.vtt

   003 Example FSM- Divide by 3 clock_en.vtt

  14 - Sequence detector using FSM with complete Design & TB

   001 Sequence detector using FSM with complete Design & TB_en.vtt

   002 Sequence detector using FSM output waveform_en.vtt

  15 - Project 1 Memory controller

   001 Memory controller with Design & TB_en.vtt

  16 - Project 2 FIFO

   001 FIFO Lecture_en.vtt

   002 Introduction to FIFO_en.vtt

   003 Write Read Operation of Normal RAM_en.vtt

   004 FIFO IO (input & Outputs)_en.vtt

   005 Block Diagram and Architecture of FIFO_en.vtt

   006 Connection of FIFO design & Test bench environment_en.vtt

   007 Verilog HDL for FIFO design_en.vtt

   008 Verilog HDL code for FIFO Test Bench_en.vtt

   009 Run the simulation and finding errors and Analyze the waveform Results_en.vtt

  17 - Project 3 Hamming code complete Design & TB for error detection & correction

   001 Hamming code complete Design & TB for error detection & correction_en.vtt

  18 - FPGA

   001 FPGA_en.vtt